1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
Recent research and development of a large-scale integration circuit (LSI) has been focused on integrating an analog circuit such as an RF circuit and a logic circuit such as a CMOS circuit in a single chip. Such an LSI having an analog circuit and a logic circuit integrated in a single chip requires a high performance capacitor satisfying both characteristics required for the analog and logic circuits. To satisfy this, it has been proposed to use a metal-insulator-metal (MIM) capacitor formed of a dielectric film (insulating film) sandwiched between metal electrodes.
Furthermore, to attain the LSI mentioned above, the MIM capacitor must have a large capacitance, which inevitably increases the area occupied by the capacitor. Thus, to increase the capacitance per unit area, a stacked capacitor having a plurality of dielectric films and electrodes stacked therein may be used.
As a conventional stacked capacitor, a chip condenser has been widely known.
FIG. 26 shows such a chip condenser. The chip condenser is formed by stacking electrodes 401 and dielectric films 402, followed by attaching metal films 403 onto both sides (edge portions) of the resultant stacked structure by means of soldering or the like.
A chip condenser having a stacked structure is described, for example, in Japanese Patent Application KOKAI Nos. 4-293215, 4-334007, and 4-356908.
On the other hand, when an MIM capacitor having a single dielectric film is formed in an LSI, the following manufacturing method is generally employed. A metal film serving as a lower electrode, a dielectric film, and a metal film serving as an upper electrode are stacked, and then these films are subjected to patterning to obtain the upper and lower electrodes. The upper and lower electrodes are patterned in different lithographic processes in order to prevent leakage current from flowing along the sidewall of the capacitor. Subsequently, an interlayer dielectric film is formed over the entire surface and then a contact hole is formed so as to reach the upper electrode and the lower electrode. A metal film serving as wiring is further formed over the entire surface, and then the metal film is patterned to form the wiring. In brief, an MIM capacitor having a single dielectric film is formed via four lithographic steps for the upper electrode, lower electrode, contact hole and wiring.
However, when a stacked capacitor having a plurality of dielectric films stacked therein is formed in an LSI, the number of lithographic steps greatly increases as the number of stacked films increases, leading to a great increase of manufacturing steps.
When a chip condenser having a construct (a stacked structure with a metal film on the edges) shown in FIG. 26 is used as the MIM capacitor for LSI, a problem occurs as shown in FIG. 27. Since the edge portions of a stacked structure formed of electrodes 411 and dielectric films 412 are not flat, the step coverage of the dielectric film at the edge portions deteriorates and an electric field converges to the edge portions, which easily increase leakage current. Therefore, the reliability and the yield of a capacitor decrease.
In summary, in the LSI having an analog circuit and a logic circuit integrated in a single chip, it is important to form a capacitor of high performance having a high capacitance without increasing the area occupied. To attain this, it is conceivable to use a stacked MIM capacitor; however the stacked MIM capacitor may cause problems of decreasing the reliability and increasing the number of manufacturing steps. Under the circumstances, it has been desired to develop a semiconductor device having a capacitor increased in capacitance per unit area without decreasing the reliability and increasing the number of manufacturing steps.